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Important Dates

Conference: May 7-11, 2012
Reg. Registration Ends: April 20, 2012
Late Registration: April 21 to May 11

RF and mm-wave Components for RADAR


Date: May 7, 2011
Time: 8:00am - 12:00pm
Instructor: Sergio Saponara and Maria Greco

Tutorial Code: T-14


In the last years the advances in radio detection and ranging technology, sustained by new achievements in the fields of signal processing and electronic components, permitted the adoption of radars in many civil and defense application. With respect to the conventional use of radar, the realization of a highly-integrated radar with limited power consumption, size, weight and cost can enable its ubiquitous adoption in new markets such as automotive safety and assisted driving systems or medical and biometric sensing, to name just a few. 

Key enabling factor for the success of this scenario is the realization, in silicon CMOS or BiCMOS technologies, of integrated transceivers for the RF radar front-end and the implementation of computing intensive radar signal processing algorithms in cost-effective and power-efficient embedded platforms.

The tutorial will start discussing the possible integration levels (radar-on-single-chip, radar-in-a-package and radar-on-single-board) and then the technologies, architectures and achievable performances when realizing in a single-chip the RF radar transceiver.

Then the main signal processing functions used in radar applications will be reviewed highlighting typical requirements in terms of instruction set, dynamic range and arithmetic accuracy, computational, communication and memory capability. To this aim radar signal processing techniques such as beam-forming, space-time adaptive processing (STAP), pulse compression, and others will be considered.

After defining the set of core functions and the relevant requirements, the different available options for their implementation in hardware platform will be discussed. The focus will be on the trade-offs between flexibility, programmability, power consumption, size and weight, complexity. Analyzed solutions range from GPU-based radar processing platforms, providing Tera floating points operations per second, to high power-efficient custom digital IP macrocells, that can be integrated as hardware accelerators in multi-core system-on-chip (MPSoC) together with processor cores. System-on-Programmable chips (SoPCs), which represent the evolution of the Field Programmable Gate Array (FPGA) devices, are emerging as a suited solution for radar signal processing since they provide configurable hardware logic, embedded DSP blocks, and soft or hard programmable cores. Beside the digital processing platform the tutorial will address also the analysis of analog/digital converter architectures meeting the requirements of ubiquitous radar applications.

The tutorial will benefit of the experience acquired in several laboratories of the University of Pisa: the signal processing and remote sensing lab, the RF and microwave IC lab and the electronic systems lab.  

Instructor Biography

Sergio Saponara graduated in Electronic Engineering cum laude and received the Ph.D. degree in Information Engineering from the University of Pisa. In 2002 he was with the Inter University Microelectronics Center (IMEC), Leuven (B), as Marie Curie Research Fellow. Since 2001 he collaborates with Consorzio Pisa Ricerche scarl (I) to technology transfer projects in the field of integrated systems. Currently, he is Professor of Electronics at University of Pisa in the field of microelectronics and electronic systems, including integrated wireless systems. He co-authored more than 150 scientific publications and 10 patents and is Associate Editor of the Journal of Real-Time Image Processing, Springer. He has also associations with the Italian National Institute for Nuclear Physics (INFN) and with the Italian inter-universitary consortium for telecommunications (CNIT). He served as special issue guest editor on international journals and as committee member of international conferences such as IEEE Euromicro DSD 2008, DATE from 2006 to 2012, IEEE MTT-S IMWS 2011.  

Maria S. Greco graduated in Electronic Engineering in 1993 and received the Ph.D. degree in Telecommunication Engineering in 1998, from University of Pisa, Italy. From December 1997 to May 1998 she joined the Georgia Tech Research Institute, Atlanta, USA as a visiting research scholar where she carried on research activity in the field of radar detection in non-Gaussian background. In 1993 she joined the Department of "Ingegneria dell'Informazione" of the University of Pisa, where she is Assistant Professor since April 2001. She is IEEE Senior Member since June 2004 and she was co-recipient, with P. Lombardo, F. Gini, A. Farina, and B. Billingsley, of the 2001 IEEE Aerospace and Electronic Systems Society's Barry Carlton Award for Best Paper. She has been co-general-chair of the 2007 International Waveform Diversity and Design Conference (WDD07), Pisa, Italy, June 2007 and she was in the Technical Committee of the 2006 EURASIP Signal and Image Processing Conference (EUSIPCO), Florence, Italy, September 2006. She is guest co-editor of the special section of the Journal of the IEEE Signal Processing Society on Special Topics in Signal Processing on "Adaptive Waveform Design for Agile Sensing and Communication," published in June 2007. She has given lectures at universities and institutions in Italy and abroad. Her general interests are in the areas of statistical signal processing, estimation and detection theory. In particular, her research interests include cyclostationarity signal analysis, DOA estimation techniques, clutter models, spectral analysis, coherent and incoherent detection in non-Gaussian clutter and CFAR techniques.